Free Download Cadence XCELIUM 23.03.009 | 3.9 Gb
Cadence Design Systems, Inc. , the leader in global electronic design innovation, is pleased to announce the availability of XCELIUM 23.03.009 (XCELIUMMAIN)is part of the Cadence Verification Suite and supports the company’s Intelligent System Design strategy, enabling pervasive intelligence and faster design closure.
Owner:Cadence
Product Name:XCELIUM
Version:23.03.009 (XCELIUMMAIN) Hotfix
Supported Architectures:x86_64
Website Home Page :www.cadence.com
Languages Supported:english
System Requirements:Linux *
Software Prerequisites:pre-installed Base Cadence XCELIUM 23.03.001 and above
Size:3.9 Gb
AVSREQ-182248 DMS_WREAL Connecting VAMS wrealmax to SV wreal1driver could give wrong result
AVSREQ-187679 PARSE_SV EXPLPA error when creating var
AVSREQ-191719 VPI_GENERAL Competition connection program VPI issue ; ERROR: VPI NOTOTI The operation vpi_iterate(vpiReg, …) is not supported for a reference handle of type vpiClockingBlock ;
ERROR: VPI NOTOTI The operation vpi_iterate(vpiRegArray, …)
AVSREQ-193591 ELAB_PERF Significant increase in the elaboration time caused by a small change in one module of the design
AVSREQ-196329 PARSE_SV Error with variable declaration
AVSREQ-200454 DEBUG_COMMAND xmsim: *F,IDAIND: Could not find location of Indago installation "" ""
AVSREQ-201994 DMS_LP_AMS Error with negative supplies in non-VCT UPF+AMS flow
AVSREQ-202729 IP_PROTECT_GENERAL MESSAGE: Unexpected signal #11, program terminated (null)
AVSREQ-203023 LP_LIBERTY LP new liberty flow: when -lps_pa_strict switch is used, this module gets classified as nonPA instead of PA
AVSREQ-203156 DEBUG_DESIGN_DATABASE Design stops responding at "Parallel LWD Data Generation" when "-lwdgen" is in Xrun option list
AVSREQ-203220 GLS_PERFORMANCE New SDF changes make elaboration to complete in 36 hours as compared to 2 hours
AVSREQ-203423 VPI_LWD vpiEnumNet should not access vpiRange
AVSREQ-204307 DMS_ELAB Elaboration exits unexpectedly with SV Bind on Spice
AVSREQ-204778 DMS_ANALOG_ELAB AMS unexpectedly exit with MESSAGE: ivia_compunit_dereference – NULL instance in xmsim.err
JIRA ID COMPONENT SUMMARY
December, 2023
Cadence’s Xcelium Logic Simulationprovides best-in-class core engine performance for SystemVerilog, VHDL, mixed-signal, low power, and x-propagation. It supports both single-core and multi-core simulation, incremental and parallel build, and save/restart with dynamic test reload. The Xcelium Logic Simulator has been deployed by a majority of top semiconductor companies, and a majority of top companies in the hyperscale, automotive and consumer electronics segments. Using computational software and a proprietary machine learning technology that directly interfaces to the simulation kernel, Xcelium learns iteratively over an entire simulation regression. It analyzes patterns hidden in the verification environment and guides the Xcelium randomization kernel on subsequent regression runs to achieve matching coverage with reduced simulation cycles. Xcelium is part of the Cadence Verification Suite and supports the company’s Intelligent System Design strategy, enabling pervasive intelligence and faster design closure.
Accelerating DFT Simulations with Xcelium Multi-Core
Are long DFT simulations posing a big challenge to meet your tight project schedules? We have a solution to accelerate the long running DFT tests. Watch this video to know how easy it is to set-up Xcelium Multi-Core to get up to 5X acceleration for a variety of DFT use cases ranging from serial and parallel ATPG to MBIST and LBIST
Cadenceis a pivotal leader in electronic design and computational expertise, using its Intelligent System Design strategy to turn design concepts into reality. Cadence customers are the world’s most creative and innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications.
