Siemens Questa Advanced Simulator 2024.1 (x64)

Questa Modeling and Verification
Today’s FPGAs (Programmable Logic Integrated Circuits) are so complex that they constitute an entire system, requiring powerful verification technology with good debugging capabilities, functional coverage assessment, and high performance.

These changes in FPGA functionality have led to the emergence of solutions using third-party IP blocks, DSPs, and multiple processors connected by modern high-speed buses.

Mentor Graphics provides FPGA verification tools and knowledge so you can produce high-quality products faster.

Verification of HDL projects Questa Core
Questa Simulation is an environment for comprehensive verification of modern digital projects of any complexity.

Verification of complex projects is based on the use of fundamental Assertions technology, on the basis of which various methodologies and additional verification technologies are built, such as functional coverage analysis, automatic test generation, statistical data collection, formal analysis, etc. and so on.

Questa Simulation – most fully supports the SystemVerilog Assertions and PSL specifications, and also includes the most complete set of tools (graphical debugging windows, import/export tools, etc.) for working with Assertions technology, and the use of ModelSim calculating kernel languages ​​for HDL modeling , which is the standard for the correctness of simulation results, does not allow us to doubt the reliability of the results obtained in Questa Simulation.

Energy Aware Simulation Questa Power Aware Simulation
Questa Power Aware Simulation is the ability in Questa Simulation to connect a description in the UPF – Unified Power Format format to an HDL project, which allows you to estimate the energy consumption of the simulated project. Power Aware Simulation is most useful in low-power systems such as battery-powered off-grid systems.

When there are several sync signals Questa CDC

A full-featured solution to the problem of verification (metastability analysis) of projects with multiple synchronization domains – Clock-Domain Crossing.

Software and hardware verification Questa Codelink
Codelink is a set of debugging tools for functional verification of processor-based designs using your processor model at the RTL or gate level.

Library of verification models Questa Verification IP – Questa VIP
Questa Verification IP are models used to verify protocols and interfaces. These models connect different levels of abstraction: RTL, TLM and system levels. Each block includes stimulus generators, signal validation, and coverage measurements for popular protocols and standard interfaces.

What’s New
official site does not provide any info about changes in this version.

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